# QP COA

Every year thousand of students appear for sppu exams,therefore it is very necessary for each and every student to be mentally prepared for the exams and for this case only we study the previous year question papers to get an insight of previous year question papers.

A good analysis of question papers can help you get a better head from others in the same exam as now you would be already prepared for those questions and that would even help you score better.The best advice that we can give you is that try to solve the maximum questions by yourself only rather than depending on solutions based books it would ultimately make your mind more lazy and you will put effort much less and the result would be that you would get less out of the subjects.

These all are as per updated 2015 pattern onwards which are of 50 marks.The question paper is divided into 8 questions of which you have to attempt any four, there is choice in every question,so among 1st two you have to attempt any one and so on.The major advantage of this pattern is that it gives you freedom to choose you among questions but each question comes with 12 to 13 marks per head so getting a question wrong in subject where start and final steps matter also count a lot.so we are also uploading a series of specially designed question bank for better preparation.

UNIT-1

Q.1.Perform the division of following numbers using non-restoring method

Dividend: 1011

Divisor   : 0011

Q.2. Draw and explain the flowchart of Booths algorithm for multiplication of signed numbers?

Q.3. Given x=1011 and y=0100 in 2’s complement representation compute the

Product p=x*y with booth’s algorithm

Q.4. Draw and explain the flowchart of Non Restoring Division

Algorithm?

Q.5. Express the following in 32bit IEEE Floating point format

a. -1.5     b. 384

Q.6. Multiply the following using booth’s algorithm

Multiplicand=+11, Multiplier= -6

Q.7. Show the general structure of IAS computer & Explain

Q.8. Draw and explain the flowchart of Restoring Division Algorithm?

Q.9. Represent (309.1875)10 in IEEE 754 Single Precision format

Q.10. show the following floating point additions are performed. Show the

result in normalized form

a. 5.566×102 +7.777x 102      b. 3.344×101+8.87710-2

UNIT-2

Q.1. List and explain the different Characteristics of Memory System?

Q.2. Explain the hierarchy of memory system?

Q.3. Explain the following Cache mapping techniques

a. Direct Mapping

b. Set Associative Mapping

c. Associative Mapping

Q.4. what is cache coherence problem? What are the solutions to cache

Coherence problem in single CPU system?

Q.5. What are the differences between SRAM & DRAM?

Q.6. List and brief different RAID?

Q.7. Write a short note on DDR3 memory organization.

Q.8 A byte addressable computer has small cache capable of holding 16 bytes, each line consists of 4 bytes. Main memory size is 256 bytes. Specify the number of bits in Tag, Line, & word offset field in main memory address?

Q.9. Find the following for Direct Mapping

Given:

•Cache Size = 8KB

•Block Size/Line Size = 64 Bytes.

•Find out the number of tag, line and word offset bits

Q.10. What are the disadvantages of Direct mapping & Associative mapping  functions?

Q.11. Explain How a memory address is mapped in to a cache memory address using 4-way set associative mapped cache. Main memory is: 64kb, Cache memory is: 2048 bytes, line size 128 bytes?

Q.12. A 4-Way set associative cache has a block size of four 16-bit words. The cache can accommodate a total of 4K such words. The main memory size is 128K words. How the processor’s addresses are interpreted

UNIT-3

Q.1. what is DMA? Explain cycle stealing in DMA.

Q.2 Differentiate between Programmed I/O and Interrupt Driven I/O

Q.3 What is machine Instruction? Explain The types of Instructions.

Q.4.A DMA module is transferring characters to memory using cycle stealing, from a device transmitting at 9600 bps. The processor is fetching instructions at the rate of 106 instructions per second. By how much will the processor be slowed down due to the DMA activity?

Q.5. Explain the general structure of I/O Module.

Q.6. What is I/O Mapped I/O & Memory Mapped I/O

Q.7. Explain the Different configurations of DMA?

Q.8. A DMA module is transferring characters to memory using cycle stealing, from a device transmitting at 9600 bps. The processor is fetching instructions at the rate of 106 instructions per second. By how much will the processor be slowed down due to the DMA activity?

Q.9 Explain the different registers of 8259 Interrupt controller

UNIT-4

Q.1 Explain the following addressing modes with one example each

a. Immediate

b. Register Indirect

Q.2. What is displacement addressing Explain its types with calculation of

Q.3. What is register organization? Explain the different types of registers?

Explain in detail

Q.4. What are different addressing modes? Explain the drawback of relative

Q.5. What are system control instructions? Explain in brief

Q.6. What are different types of operations performed by microprocessors?

Q.7. Show how to implement the following statement using an accumulator machine (1 address machine): a = a + b + a * c Instructions available are: LOAD, MUL ADD, STORE

Q.8. For a given ISA, if the computer has 2 operand machine language instructions and Instruction size: 16-bit Number of registers: 16 Size of each register: 16-bit Find how many opcodes are available for this 2 operand machine(i.e.2 address machine)

UNIT-5

Q.1.  What are the various hazards in Instruction pipelining? Explain

Q.2. Write a short note on superscalar execution and superscalar      implementation

Q.3. Explain The Instruction Cycle in detail

Q.4 List and Explain the various ways in which an instruction pipeline can deal with conditional branch instruction

Q.5 What is pipelining ? Explain how it affects the speed of execution

Q.6 Explain with example the working of multistage pipelining.

Q.7. Consider the following sequence of instructions:

I1: add R1, R0, #20 (R1 R0 + 20)

I2: mul R2, R3, #2 (R2 R3*2)

I3: and R4, R1, R2 (R4 R1 and R2)

I4: add R5, R4, R2 (R5 R4 + R2)

These instructions are executed in a computer that has a four stage pipeline (Fetch, Decode, Execute, Write. Assume that all stages for all instructions requires one cycle each, except the Execution stage of multiply instruction which requires two cycles.

Draw a diagram to describe the operation being performed by each pipeline stage during each clock cycle. Show the stalls in pipeline, if any.

Q.8. Example Program

–R3= R3 + R5; (I1)

–R4= R3 + 1; (I2)

–R3= R5 + 1; (I3)

–R7= R3 + R4 (I4)

Identify the hazards among above instructions I1 and I2 ? I3 and I4 ?

I2 and I3 ? I1 and I3 ?

UNIT-6

Q.1.  Explain sequence of operations needed to perform processor functions

(i) Fetching a word from memory

(ii) Performing an arithmetic or logical operation.

Q.2. Compare:

(i) Horizontal and vertical microinstruction representation

(ii) Hardwired and micro programmed control unit.

Q.3. Explain Memory read cycle Micro operations

Q.4. Explain Memory write cycle Micro operations

Q.5. Write the control sequence for the following instruction for the single

bus organization :

SUB (R3), R4    Where R3 is source register and R4 is destination register.

Q.6. Write the control sequence for the following instruction for the single bus organization

Q.7. Explain Wilkes Control method for micro-programmed control unit

Q.8. Explain with suitable block diagram design of CPU using hard-wired   control method.

Q.9. How are the control signals generated in hardwired control unit ?

Q.10. Draw and explain single bus organization of the CPU and write the control sequence for the Unconditional branch instruction.

Q.11. Explain in detail micro instruction sequencing organization

Q.12. Draw and explain single bus organization of the CPU, showing all registers and Data paths

Q.13. Draw and explain general block diagram of the micro programmed control unit.