Every year thousand of students appear for sppu exams,therefore it is very necessary for each and every student to be mentally prepared for the exams and for this case only we study the previous year question papers to get an insight of previous year question papers.

A good analysis of question papers can help you get a better head from others in the same exam as now you would be already prepared for those questions and that would even help you score better. The best advice that we can give you is that try to solve the maximum questions by yourself only rather than depending on solutions based books it would ultimately make your mind lazier and you will put effort much less and the result would be that you would get less out of the subjects.

These all are as per updated 2015 pattern onwards which are of 50 marks. The question paper is divided into 8 questions of which you have to attempt any four, there is a choice in every question, so among 1st two you have to attempt anyone and so on. The major advantage of this pattern is that it gives you the freedom to choose you among questions but each question comes with 12 to 13 marks per head so getting a question wrong in a subject where the start and final steps matter also count a lot.so we are also uploading a series of a specially designed question bank for better preparation.

**Unit – I (Combinational Logic Design)**

1. Convert the following numbers into its equivalent hexadecimal, decimal, and binary

number (show step by step process of conversion)

a. (357.2)8 b. (457.54)8

2. Represent the following decimal numbers in single precision floating point format

a. 255.5 b. 110.65

3. Subtract following decimal number using 9’s, 10’s, 1’s and 2’s complement method

49.54 and 68.75.

4. Express the following decimal numbers in 8421 BCD code, XS-3 code, 2421 code,

5211 code, 6423 code, 8421 code.

a. 807 b. 158.7

5. Perform the following operation in BCD and XS-3 codes.

a. 275 + 493 b. 88.7 + 265.8 c. 920 – 356 d. 634.6 – 328.7

6. Draw the logic diagram that implements :

a. = + +

b. = ̅ +

+

c. Y = (X

+X++)

7. Solve following Boolean equations and implement using NAND and NOR logic.

= ( )(

)+

8.
Minimize the following logic functions and realize using *NAND/NOR *gates.

a. ( ) = Σ (1, 3, 5, 8, 9, 11, 15) + (2, 13)

b. ( ) = Π (1, 2, 3, 8, 9, 10, 11,14) ∙ (7, 15)

9. Reduce the following expression using K-map.

a. =

+ +

+

+ ̅

b. = (̅+ )( + +

)( + ̅)( + + )

c. = (̅+ + ̅+ )(0 + ̅

)

10. Minimize the following expressions using K-map and realize using NOR gates only

i.
*f *(A,B,C,
D)=П M(2,3,5,6,7,9,10,11,13,14,15)

ii.
*f *(A,B,C,
D)=П M(2,7,8,9,10,12)

11. Implement full adder using half adder.

12. Implement and Realize full subtractor and full adder using 3 line to 8 line decoder.

13. Design one digit parallel subtractor using 2’s compliment system.

14.
Design combinational circuit that multiplies two 2-bit numbers *a**1**a**0 *and *b**1**b**0 *to

produce
a 4-bit product *c**3**c**2**c**1**c**0*, use and gates and half adder.

15. Realize logic expression using 8:1 MUX.

( ) = Σ (0, 3, 5, 6, 9, 10, 12, 15)

( ) = ̅ + + + ̅

16. What do you mean by multiplexer tree explain with example.

17.
Implement the following logic functions using single *8:1 MUX*.

i. ( ) = Σ (1, 3, 4, 11, 12, 13, 14, 15)

ii. ( ) = Σ (0, 2, 3, 5)

18.
Design 4-bit Excess-3(*XS-3*) to *BCD *code converter and implement
using minimum

numbers of gates.

19.
Design gray code to *BCD *code converter and implement using EX-OR or
EX-NOR

gates.

20. Design 4 bit BCD code to excess-3 code converter and implement using logic gates.

21. Design one digit-BCD to gray code converter using minimum number of logic gates.

22. Design a combinational circuit to produce 2’s complement of 4 bit binary number.

23. Design a circuit to detect decimal numbers 0, 1, 2, 3, 7, 8, 9 form 4 bit excess 3 code

input.

24. Design a combinational circuit that accepts 3 bit BCD number and generates an

output binary number equal to the square of the input number.

25. Design a logic circuit with 4 inputs A, B, C, D that will produce output ‘1’ only when

adjacent input variables are 01. A and D are adjacent. Implement using universal

gate.

26. Design odd parity generator for 4 bit input using IC 74180.

27. What is priority encoder explain with any one priority encoder.

28. Explain function table &working of Decimal to BCD priority Encoder.

29. Design 8-Line to 256-Line Decoder using 4-Line to 16-Line Decoder.

30. Design BCD to seven segment decoder.

31. Design 4-to 16- line decoder with active low outputs

a. = Σ (0, 3, 5, 6, 9, 10, 12, 15)

b.
*f**2 *=П M(0,1,3,7,9,10,11,13,14,15)

32. What is digital comparator? Design 2-bit digital comparator and implement using

logic gates.

33. Design a 2 bit magnitude comparator using suitable decoder.

34. Design a 5 bit comparator using a single 7485 and one gate.

35. What is ALU? Write a short note on it.

36. Realize the following logic functions using 4 to16 decoder with active low outputs.

i. = Σ (0, 3, 5, 6, 9, 10, 12, 15)

ii. = Π (0, 1, 3, 7, 9, 10, 11, 13, 14, 15)

37. Simplify the following function using Quine-McCluskey Method.

i. ( ) = Σ(0,1, 2, 3, 5, 7, 8, 9, 11, 14)

38. Define hazards. Explain types and hazard.

39. Design & explain working of Excess-3 adder for 9+4 addition.

**Unit – II (Sequential Logic Design)**

1. Draw and explain sequential logic circuits.

2. Compare combinational and sequential logic circuits.

3. Compare synchronous and Asynchronous sequential logic circuits.

4. Draw and explain 1 bit memory cell.

5. Differentiate between latch and flip-flop.

6. Draw and explain SR flip flop using NAND gate.

7. Draw and explain JK flip-flop and master-slave JK flip-flop using NAND gate.

8. Explain how race around condition is avoided in JK flip flop.

9. Explain triggering modes.

10. Draw truth table of SR, JK, D and T flip flop.

11. What is the use of preset and clear function?

12. What is excitation table and write excitation table for SR, JK, D and T flip flop?

13. State the characteristics equations of all flip flops.

14. Convert:

i. JK FF to SR FF

ii. D FF to SR FF

iii. T FF to SR FF

iv. SR FF to JK FF

v. D FF to JK FF

vi. T FF to JK FF

vii. SR FF to D FF

viii. JK FF to D FF

ix. T FF to D FF

x. JK FF to T FF

xi. D FF to T FF

xii. SR FF to T FF

15. What is clock skew and clock jittering in synchronous circuits?

16. Design mod 5 ripple counter using JK flip flop.

17. Design mod 10 up/down ripple counter using D flip flop.

18. Design and implement synchronous mod-6 counter using following FFs, undesired

states must always go to zero (000) on the next clock pulse.

i. JK FF

ii. D FF

iii. UP and down using T flip flop

19. Design mod 8 counter and mod 64 counter using IC 7490.

20. Design mod 12 and mod 50 counter using IC 7493.

21. Discuss the problems of asynchronous counter and give the proper solution.

22. What is lock out condition and how to avoid it.

23. Design and implement synchronous counter for 0-2-4-6-7-0 states using J-K flip-flops

avoid lock out condition.

24. Design and explain 4 bit UP/DOWN ripple counter with control for UP/DOWN

counting.

25. Draw and explain the operation of universal shift register with its applications.

26. Draw and explain ring counter with timing diagram.

27. Draw and explain twisted ring counter with timing diagram.

28. What are the applications of flip flop?

29. Design pulse train generator using following method to generate the pulse train

101110…

i. Direct logic

ii. Indirect logic

iii. Shift register

**Unit – III (Algorithmic State Machines)**

1. Explain Finite State Machine with diagram.

2. Explain following terms related state machine.

a) State diagram b) State table c) State reduction

3. Classify finite state machines.

4. Compare Moore and Mealy machines.

5. Explain Moore machine with example.

6. Explain Mealy machine with example.

7. Explain state assignment with thumb rules.

8. Compare Mealy and Moore sequential machine with reference to block diagram,

state diagram, hardware and speed.

9. State the steps for synthesis of FSM using Moore and Mealy machine.

10. Draw state diagram and state table for serial adder and odd parity-bit generator.

11. Design and implement 1011 sequence detector using Moore machine and SR Flip

flop.

12. Design and implement 1101 sequence detector using Mealy machine and JK flip

flop.

13. Implement following state diagram using D FF.

14. What is VHDL? Write its features?

15. Explain following statements with examples

a. Process b. case c. wait

16. Describe dataflow modeling style of VHDL with example.

17. Describe behavioral modeling style of VHDL with example.

18. Describe structural modeling style of VHDL with example.

19. Explain the difference between concurrent and sequential statements.

20. Explain loop statement with example.

21. Differentiate between signals and variables.

22. Write a note on data objects and data types in VHDL.

23. State different types of operators in VHDL.

24. Explain syntax of process statement. What are the statements which can be used

under the process?

25. Write a VHDL code for 2-bit comparator using behavioral style.

26. Write a VHDL code for negative edge triggered D flip flop with synchronous active

low reset input.

27. Write a VHDL code for full subtractor using structural modeling.

28. Write a VHDL code for 3:8 decoder using case statements.

29. Write a VHDL code for 8:1MUX using behavioral modeling.

30. Write a VHDL code for 4-bit ripple up-down counter using behavioral style.

31. Write VHDL code for 4-bit ALU with minimum 4-arithmetic and 4 logical

operations using behavioral modeling.

32. Write VHDL code for JK flip-flop with asynchronous set/reset.

33. Compare IF and CASE statement. Write down VHDL code for 16:1 MUX using

4:1MUX, Use structural style of modeling.

**Unit – IV (Programmable Logic Devices****)**

1. What is programmable logic device? State merits and demerits of PLDs.

2. What is different combinational PLDs. Explain with difference?

3. Explain ROM with internal organization.

4. Give logical representation of 32 x 4 ROM.

5. Implement 3-bit binary to gray conversion using PROM, PAL and PLA with

programming table.

6. Implement following function using PAL, PLA, PROM

F1 (A, B, C) =Σm (0, 3, 4, 7)

F2 (A, B, C) =Σm (1, 2, 5, 7)

7. Design 7 segment decoder using PLA.

8. Design BCD to Excess 3 code converter using suitable PLDs.

9. Design 2K x 8 memory using 1K x 4 memory.

10. Design 16K x 8 using 4K x 8 memory chip.

11. Compare PAL, PLA and PROM.

12. Obtain 2048 x 8 memory using 256 x 8 chips.

13. Explain the classification of memories.

14. Classify ROM and explain each type with merits.

15. Draw the basic structure of CPLD and explain its features.

16. Draw the basic structure of FPGA and explain its features.

17. What is mean by SRAM and DRAM? Explain in detail. Also compare SRAM and

DRAM.

**Unit – V (Logic Families)**

1. Classify the ICs and explain with merits and demerits.

2. Write a short note on classification of logic families in detail.

3. State and the explain characteristics of digital ICs.

4. Explain the characteristics of TTL logic families.

5. Draw and explain two input totem pole output TTL NAND gate.

6. Draw and explain CMOS inverter.

7. Draw and explain TTL circuit for 2 input NAND gate with open collector output.

8. Explain the following characteristics of CMOS logic family

a) Power dissipation

b) Propagation delay

c) Noise margin

d) Fan in and fan out

9. Give comparison between TTL, ECL, CMOS logic families.

10. Draw and explain the working of 2/3 input CMOS NAND gate.

11. Draw and explain the working of 2/3 input CMOS NOR gate.

12. Explain open drain CMOS.

13. What is wiredAND logic and unconnected inputs?

14. With neat diagram explain the interfacing of the CMOS as a driver and TTL as load.

**Unit – VI (Microcontrollers)**

1. Compare Microcontroller and Microprocessor.

2. Explain 8051 architechture.

3. Write the SFR list of microcontroller

4. Explain any 3 addressing modes of microcontroller.